1. Technical Field
The present invention relates to a voltage generator, and more particularly, to a substrate bias voltage generator and a method of generating a substrate bias voltage in which voltages having different levels can be supplied in normal and refresh operations in a semiconductor memory apparatus.
2. Related Art
In general, a sense amplifier of a semiconductor memory apparatus senses cell data when a voltage difference ΔV between an amount of electric charges, which are applied to a bit line according to an amount of electric charges stored in a cell, and an amount of electric charges, which are applied to a bit line bar by charge sharing, becomes sufficiently larger than an offset voltage of the sense amplifier. The voltage difference ΔV between the bit line and the bit line bar can be expressed by the following equation 1.ΔV=(VCORE−VBLP)/{1+(CB/CC)}  [Equation 1]
Here, the voltage VCORE is a sense amplifier driving voltage, and the voltage VBLP is a bit line precharge voltage. As can be seen in Equation 1, in general, as a CB (bit line capacitance) decreases and a CC (cell capacitance) increases, the voltage difference ΔV increases. As a result, a precise sensing operation can be performed.
FIG. 1 is a timing diagram illustrating an operation of a sense amplifier in a conventional semiconductor memory apparatus.
For example, during a precharge operation, both the bit line and the bit line bar are precharged to a precharge voltage VBLP. Assuming that the cell data is at a high level, when a word line WL is activated, electric charges stored in the cell start to charge a bit line BL1 and a bit line bar BLb1 so as to be shared therebetween. Then, after a sensing period of time passes, the voltage of the bit line BL1 increases by ΔV1 with respect to the bit line bar BLb1. Then, by means of a sense amplifier enable signal, the voltage of the bit line BL1 rises to a VCORE level and the voltage of the bit line bar BLb1 is amplified to a ground potential GND level.
On the other hand, assuming that the cell data is at a low level, when the word line WL is activated, the electric charges stored in the cell charge a bit line BL0 and a bit line bar BLb0 so as to be shared therebetween. Then, after the sensing period of time passes, the voltage of the bit line BL0 falls by ΔV0. Then, the voltage of the bit line BL0 is amplified to the ground potential GND level and the voltage of the bit line bar BLb0 is amplified to the VCORE level.
Here, in order to perform a precise sensing operation, the values ΔV1 and ΔV0 should be larger than the offset voltage of the sense amplifier. If the voltage difference between the bit line and the bit line bar is not sufficient, an error occurs in a sensing result of the sense amplifier.
Therefore, the voltage differences need to be made sufficiently large by decreasing the CB value or increasing the CC value in Equation 1. A method of decreasing the CB value includes a method of controlling a voltage, which is applied to the sense amplifier and a substrate in a cell array region, to have a negative value. When this method is used, the CB value is reduced and the threshold voltage of a cell transistor increases. This reduces the electric charges stored in the cell from leaking through a channel, and accordingly, a refresh characteristic can also be improved.
However, as semiconductor memory apparatuses are highly integrated, the semiconductor memory apparatuses are manufactured using a shallow junction technique. When the shallow junction technique is applied, the impurity concentration in source/drain regions and the body increases, and as a result, the leaking between the source/drain regions and the body significantly increases. Such a leaking phenomenon increases as a voltage applied to the body becomes smaller (that is, as a negative voltage becomes larger), which deteriorates the refresh characteristic.
On the other hand, the threshold voltage of the cell transistor increases as an absolute value of a substrate bias voltage applied to the body becomes larger. Accordingly, in order to sufficiently store the cell data again through a refresh operation, a problem occurs in that a gate voltage should be sufficiently high.
In other words, in the case in which the substrate bias voltage is controlled to have a negative value, the data storage capability of a cell is improved; however, if the control is not made such that the gate voltage has a high value in order to perform the refresh operation, the refresh efficiency is lowered.